Accompanied with the development of realtime applications of information processing devices, such as audio/video realtime playback, video retrieving and recording of multimedia applications, and continual upgrading of CPUs, data transmission rates of memory devices for the information processing devices are increasingly getting higher as well.
In a conventional synchronous dynamic random access memory (SDRAM), one of reading and writing is allowed at a rising edge of every square wave within a clock cycle. When writing and reading are simultaneously requested, one of them is performed after the other is completed. To overcome such shortcoming, a double-data-rate (DDR) SDRAM is designed to provide reading and writing respectively at a rising and a falling edge of every square wave within on clock cycle, so that the data transmission rate of the DDR SDRAM is double. Moreover, DDR2 SDRAM and DDR3 SDRAM, successive to the DDR SDRAM, provide even higher performance and lower voltage, and are capable of increasing the data transmission rate to four and eight times that of the original SDRAM.
To enhance power-saving and transmission rate, the new-generation DDR2 SDRAM and DDR3 SDRAM have different packages and I/O arrangements from the conventional DDR SDRAM, and add numerous memory functions. For example, the DDR2 SDRAM is provided with ODT (On-Die Termination), OCD (Off-Chip Driver), posted CAS (Column Address Strobe) and AL (Additive Latency) controls; the DDR3 SDRAM is further provided with CWD (Column Write Delay), Reset, ZQ (zero-quotient) calibration, SRT (Self-Reflash Temperature) and PASR (Partial Array Self-Refresh) functions.
In practice, an electronic device may adopt different types of SDRAM based on its actual requirements. For example, the faster DDR3 SDRAM may be used in high-end electronic devices that require a higher memory data transmission rate; the slower DDR SDRAM may be used in low-end electronic devices that require a lower memory data transmission rate. However, because the I/O interfaces and configurations of the DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM are different, different designs corresponding to the DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM are needed. That is to say, in the prior art, I/Os of a chip are only compatible with one of DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM.
Further, it is to be noted that different types of SDRAM (e.g., DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM) have different electrical characteristics and speed requirements for a same memory function (e.g., data strobe, data address, clock). Hence, to fulfill different requirements of different types of SDRAM when incorporating DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM into chip designs, much time and effort is needed to tune the electrical characteristics and speeds to ideal values, thereby resulting in a time-consuming and lengthy design flow.
Therefore, there is a need for a universal I/O generating apparatus and method for overcoming the above issues.